class HDLPortInfo():
    def __init__():
        IODirection = ''
        IOPortName = ''
        IOPortNameLength = ''
        IOBusPart = ''
        IOBusMSB = ''
        IOBusLSB = ''
        IOIsBus = False
    def HDLineRegulate(self,HDlineOriginal, languageCommentKey):
        HDline = ""
        ver_line_noComment=''
        if HDlineOriginal.find(languageCommentKey):
            ver_line_noComment = HDlineOriginal[0: HDlineOriginal.index(languageCommentKey)]
        else:
            ver_line_noComment = HDlineOriginal
        
        # //删除横向制表符
        HDline = ver_line_noComment.replace("\t", "")
        # //删除所有空格，逗号，分号
        HDline = HDline.replace(" ", "")
        HDline = HDline.replace(",", "")
    #   //  HDline = HDline.Replace(";", "");

        return HDline


    # VHDL processing
    def vhGetPortDecalration(self, vhOriginalList):
        reguList = []
        onlyPortDef =[]
        for vh_line in vhOriginalList:
            vh_lineRegu = HDLineRegulate(vh_line, "--")
            if (vh_lineRegu!=""):
                 reguList.append(vh_lineRegu)
        # //提取entity定义
        startEttyCapted = False
        endEttyCapted = False
        ettyStrSum = ''

        for vh_line in reguList:
        if startEttyCapted == False:
                
            vh_line_lower = vh_line.lower()

        if vh_line_lower.index("entity") == 0:
        {
            startEttyCapted = True;
            onlyPortDef.append(vh_line);
            ettyStrSum = ettyStrSum + vh_line.lower() ;
        }
        elif 
        
                   



class fileOutPutConfig():
    def __init__():
        b_AddModuleOrEntityAndComponent = ''
        b_AddSignalDefinition = ''
        b_AddInstantiationTemplate = ''
        b_InsertSameNameSignal = ''
        b_AddTestBench = ''
